The Universal Chiplet Interconnect Express Consortium was formed in March of 2022, in an effort to standardize chiplet die-to-die interconnect technology and help establish an open chiplet ecosystem. The initial members of the consortium included a number of industry heavyweights, including ASE, AMD, Arm, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC, to name a few.
The initial UCIe 1.0 spec outlines a standardized die-to-die interconnect with physical layer, protocol stack, software model, and compliance testing. It was devised to afford members the ability to mix and match chiplet components from multiple vendors, and to facilitate and enable more rapid System-On-A-Chip (SoC) design and development. Since then, the UCIe 2.0 spec has been released, which expands on the original with support for manageability system architectures and more advanced 3D packaging technologies.
A few days ago, Synopsys propelled UCIe even further, with the launch of its own IP solution operating at up to 40 Gbps per pin, which results in 25% higher bandwidth than the current UCIe spec. The Synsopsys 40G UCIe IP affords up to 12.9Tbps per mm of data to efficiently travel between heterogeneous and/or homogeneous chiplet dies, with minimal silicon footprint. Higher bandwidth between chiplets is critical for enabling next-generation processor designs, and advanced AI and automotive ADAS systems, which must move massive amounts of data. Of note is that, despite its higher performance, Synopsys’ IP remains compliant with the UCIe 2.0 specification.
“Launching the industry’s first complete 40G UCIe IP solution underscores Synopsys’ continued investment in advancing semiconductor innovation,” said Michael Posner, vice president of IP product management at Synopsys. “Our active contribution to the UCIe consortium has enabled us to deliver a robust UCIe solution that helps our customers successfully develop and optimize their multi-die designs for high-performance AI computing systems.”
Synopsys’ 40G UCIe IP solution consists of controller, PHY, and verification technology, with integrated signal integrity monitors (SIMs) and testability features to simplify bring-up and debugging, and ultimately improve reliability. The 40G UCIe IP is also built on the company’s silicon-proven architecture, which has already shown interoperability with advanced processes and supports all common SoC interface fabrics.
There are a number of quality-of-life improvements that come as part of this launch as well. Synopsys’ 40G UCIe IP solution has features that ease integration, including a single 100MHz reference clock for all UCIe PHYs that eliminates the need for additional high-frequency system PLLs. And it also supports today’s standard and advanced packaging technologies, to afford customers flexibility when designing and developing next-gen chips for a wide variety of markets and use cases.
The Synopsys 40G UCIe IP will be available later this year, for multiple foundries and chip fab process technologies.
