For two decades the semiconductor industry has been racing toward a wall: the point at which transistors get so small that physics itself stops cooperating. On Thursday, IBM said it had found a way around that particular wall, unveiling what it calls the world’s first sub-1 nanometer chip technology. It’s built on a new transistor design at the 0.7 nm node—7 angstroms, a scale measured in the width of individual atoms.
This is an impressive chip, cramming nearly 100 billion transistors onto a piece of silicon roughly the size of a fingernail. According to IBM’s technical results, this translates to up to 50% more performance, or 70% better energy efficiency than its 2 nm predecessor.
The key highlights at a glance:
- 100 billion transistors
- Takes up only a fingernail-sized space
- Twice the density of IBM’s 2 nm node chip
- Transistors are vertically stacked and staggered in a 3D chip architecture called nanostack
- Up to 50% higher performance
- Up to 70% greater energy efficiency
- Will enable 40% scaling in SRAM, which IBM says is the biggest leap in at least a decade
The promised efficiency gain matters: the generative-AI boom has turned chip power consumption into one of the computing industry’s biggest problems, with data centers straining grids and hunting for water for cooling. A chip that does the same work for 70% less energy is will help with both problems.
The breakthrough depends on a new architecture IBM is calling “nanostack,” what it says is the industry’s first three-dimensional nanosheet-based transistor design. Very simply, rather than continuing to shrink transistors across a flat plane, IBM vertically stacked and staggered them, using 3D sequential integration to pack more computing into the same footprint. AMD, Intel, Nvidia already ship “3D stacked” chips, but they’re stacking packages, not transistors. IBM’s nanostack is doing it at the transistor level, which is significantly harder.
There’s another benefit: because each layer is built separately, engineers can mix and match different materials in each one, tuning performance and power independently. IBM says it has already validated the approach with working CMOS inverters and demonstrated 40% scaling in SRAM, the fast on-chip memory that feeds data-hungry AI workloads.
“With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” said Jay Gambetta, director of IBM Research and an IBM Fellow, calling it “a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms.”
For years, we’ve wondered aloud whether Moore’s Law (the steady, decades-long cramming of more and more transistors onto chips) was finally running out. IBM’s nanostack roadmap projects at least another decade of scaling below 1 nm, suggesting the runway is longer than the skeptics feared.
IBM isn’t building this alone.
The work is being done at a leading research facility in Albany, New York, soon to house an ASML-developed High-NA EUV lithography tool—the cutting-edge machine needed to print circuits this small.
Partners including Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions are helping develop the processes around it, work IBM says has already produced functioning devices.
At this point the sub-1 nm chip is a research achievement, not a shipping product. IBM says it sees a path to production within five years. If it achieves that or sooner – and if competitors don’t get there before Big Blue – this is likely to be a significant and profitable product.
