In April this year, the Storage Networking Industry Association, SNIA, announced the launch of the MRAM Alliance Special Interest Group (SIG). This initiative aims to accelerate the adoption of Magnetoresistive Random-Access Memory, MRAM, by uniting industry leaders, from foundries to system designers, to develop a robust ecosystem and to standardize important technologies. The SIG promotes MRAM for AI, automotive and data center applications and is working with the IEEE Standards Association to create standards addressing the perception of risk regarding sensitivity to external magnetic fields.
The SIG has also created an Interface subgroup to drive new interface standards to make MRAM easier to implement. I recently spoke with Steffen Hellmold, who is working with MRAM company, Everspin, on important MRAM memory system architectures.
MRAM and other persistent memories are becoming an important element in memory solutions for consumer, industrial, hyperscale and space datacenter applications. MRAM in particular has replaced NOR flash in many devices for code storage and supplemented or replaced SRAM for persistent memory and storage. As the volume of MRAM production goes up, the costs will decline and with advances in technology that will increase performance, MRAM could displace DRAM in some applications.
Steffen told me that MRAM has never had an interface designed for it, but always used interfaces developed for other types of memory technology. Everspin has been shipping xSPI and SRAM compatible MRAM for 20 years. Additionally, the company has been selling since 2017 DDR4 MRAM with adaptations of the DDR 4 interface to support MRAM rather than DRAM. DDR4 MRAM is used in IBM’s FlashCore modules as a an ultra-fast, non-volatile write cache and data buffer in conjunction with NAND flash.
This was made possible because of the Xilinx, now AMD, UltraScale+ platform that enabled a software-controlled host controller. However, Steffen pointed out that in later DDR versions, such as LPDDR5 and LPDDR6, host controllers are currently only available as hard IP, which doesn’t allow modifying it to support the differences between MRAM and DRAM.
He said that a JEDEC standard to support new persistent memories, such as MRAM is needed. This would be a modification of existing and future standards so that architectural features such as page size configurations and timing can be broadened so they work with MRAM as well as DRAM.
The SNIA MRAM SIG is evaluating how to create a JEDEC standard to enable persistent working memory that can support read and write and ultimately boot from a single LPDDR interface.
Likewise, the use of CXL for memory expansion and disaggregated far memory to support software-controlled infrastructure will be a benefit for MRAM and other persistent memories. MRAM can also be used as a memory in a chiplet architecture where various computing functions are made on separate die and then connected in a package with a high-performance interface. MRAM can be used to augment or replace conventional memories such as SRAM, DRAM and flash in a chiplet architecture and indicated in the image below.
The point of the image above is to show MRAM replacing one or more conventional memories in a chiplet package, depending upon the application requirements.
There is also ongoing work in other industry groups such as the Open Compute Platform, OCP, to develop chiplet interface standards for memories, including persistent memory.
The SNIA MRAM Special Interest Group will explore, through its interface subgroup, an architectural ecosystem enabling MRAM connectivity via LPDDR, CXL and chiplet interfaces.
