At the 2026 FMS Conference in Santa Clara California, stacking DRAM and NAND flash chips and making semi-customized products that expand the storage/memory hierarchy was a major topic. This piece will focus on the efforts to create high bandwidth flash, HBF, to support AI inference applications.
SK hynix partnered with Sandisk to develop HBF, starting in early 2025 We will show SK hynix FMS material first, including their NAND and DRAM advances, as well as HBF and then show Sandisk presentation materials on their NAND products and HBF.
During the SK hynix keynote, Kang Uksong, VP and Head of Next Generation Product Planning at SK hynix introduced their own new tiers in the memory and storage hierarchy, shown below. They Introduced new memory tiers between traditional layers to maximize xPU performance, ensure QoS, and optimize TPS/MW and Token/$.
These include G0.5 which sits above HBM at G1 using 3D-stacked DRAM and delivering near-SRAM bandwidth with DRAM-class capacity, G1.5, which is HBF with about 1TB capacity and Tb/s scale bandwidth and G2.5, a CXL-pooled memory enabling cost-effective scalability with multiple TBs of capacity.
The figure below shows SK hynix’s latest memory and storage solutions shown at the FMS.
The figure below shows more details about the G0.5 tier of 3D stacked DRAM versus SRAM and HBM. This product may be similar to the stacked DRAM product that Samsung showed in their FMS keynote.
The figure below shows more details about the G1.5 tier, high bandwidth flash, HBF.
Kim Chunsung, EVP, SK hynix, spoke about AI inference. The figure below shows two types of storage requirements for inference running on personal devices, one for persistent assets such as models, RAG and user data and the other to store the dynamic runtime state to improve inference performance to store KV cache, agent states and metadata.
He also said that enterprise workloads are becoming more diverse, as shown below, with various storage requirements. This is a big driver for the new memory and storage tiers.
He showed a timeline for the HBF activity, including the announcement of the 0.7 HBF standard at the 2026 FMS Conference. The full HBF spec if expected to be released in early 2027 with HBF samples available in early 2028 and full HBF flash production after that.
Khurram Ismail, Chief Product Officer at SanDisk talked about their vision of additional layers in the storage and memory hierarchy for storing persistent KV cache as shown below.
He also showed Sandisk 218-layer BiCS8 eSSDs for compute and storage, shown below. The compute eSSD has TLC NAND flash for higher endurance with capacities up to 32TB while the storage eSSD uses QLC NAND flash with capacities up to 256TB.
Sandisk’s Alper Ilkbahar, CTO, talked about their latest 332-layer BiCS10 chips that have 1Tb capacity using TLC NAND and 2Tb with QLC NAND. He also discussed high bandwidth flash, HBF, which the company is pursuing with SK hynix and others. HBF stacks and connects NAND chips in a way similar to the way that DRAM chips are stacked and connected in high bandwidth memory, HBM.
This results in a higher performance NAND package that provides high non-volatile storage capacities to supplement or replace HBM. The chart below shows how HBF can be combined with HBM in various ways or used by itself to support AI XPUs, depending upon the application.
For 4TB HBF only memory with 4-GPUs compared to 192GB HBM with 8 GPUs the tokens generated per second was almost the same, resulting in 2X GPU efficiency and lower total cost.
He also showed a roadmap for the HBF Consortium to support this effort shown below as well as announced a new member of the consortium board, Jim Keller, CEO of Tenstorrent, who will join David Patterson from Berkeley and Raja Koduri, Founder and CEO of Oxmiq Labs. The first HBF specification was released at the FMS Conference.
The HBF capacity specifications enable up to 512GB based on two stack configurations (8-high and 16-high NAND dies). Bandwidth is categorized into three grades (Grade1~3), delivering scalable performance from approximately 0.4TB/s to 3.0TB/s. In addition, HBF adopted the UCIe interconnect to link HBF packages to processors.
SK hynix and Sandisk showed their new DRAM and NAND products at the 2026 FMS Conference as well as announced the initial high bandwidth flash, HBF, specification and roadmap.